With the rapid development of integrated circuits (IC) manufacturing technology, the IC integration density continues to increase and the IC feature sizes continue to shrink. As IC devices are getting denser and smaller, metal oxide semiconductor (MOS) transistors become more widely used in IC devices. MOS transistor performance may affect IC performance. Among many parameters of MOS transistors, the threshold voltage (Vt) is the most important one.
Further, in order to improve the overall IC performance and the flexibility to handle mixed signals, most ICs include many individual semiconductor devices with various threshold voltages to enable the multi-threshold voltage capability of ICs.
In the conventional fabrication process of forming multiple semiconductor devices with various threshold voltages, the gate oxide layer, the channel region, the well region, and the source/drain regions may be doped with various types, energies, and dosages of impurity ions. In addition, work function layers with various thicknesses may be formed to adjust the threshold voltages of semiconductor devices.
However, with the reduction in size of semiconductor devices, the requirements for the accuracy of the ion implantation energy level and dosage become more stringent and difficult to satisfy. The ion implantation method for adjusting the work function of semiconductor devices may reduce the gate electron mobility and may worsen the performance of the semiconductor devices.
Work function layers with various thicknesses may be formed to adjust the threshold voltages of corresponding semiconductor devices. Referring to FIG. 1, a semiconductor substrate 10 has three active regions, a low threshold region I, a standard threshold region II and a high threshold region III. A dielectric layer 20 is formed on the semiconductor substrate 10. A first work function layer 21 is only formed on the dielectric layer 20. A first mask 22 is formed on the low threshold region I to protect the first work function layer 21 on the low threshold region I.
Referring to FIG. 2, after the first mask 22 is removed, a second work function layer 23 is formed on the first work function layer and on the standard threshold region II and the high threshold region III of the semiconductor substrate 10. A second mask is formed on the low threshold region I and the standard threshold region II to protect the second work function layer 23 on the low threshold region I and the standard threshold region II. The remaining second work function layer 23 is removed.
Referring to FIG. 3, a third work function layer 25 is formed on all three regions. In conclusion, the formed semiconductor device has a successively decreased thickness from the low threshold region I to the standard threshold region II to the high threshold region III. The thicker work function layers correspond to lower threshold voltage. The formed semiconductor device has a successively increased threshold voltage from the low threshold region I to the standard threshold region II to the high threshold region III. The above process is complicated due to the requirements for multiple masks, multiple work function layers and multiple removal processes.
The disclosed devices and methods are directed to solve one or more problems set forth above and other problems in the art.